1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for fabricating a bipolar transistor.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
In general, bipolar transistors offer relatively fast switching speeds and therefore, are often used in integrated circuit design. However, the fabrication of bipolar transistors typically requires several steps, thereby increasing the complexity of the fabrication process of the integrated circuit. For example, a bipolar transistor is generally fabricated by forming an epitaxial layer upon a semiconductor topography followed by the deposition of silicon dioxide and, in some embodiments, the deposition of silicon nitride. Consequently, a conductive layer formed above the dielectric layer/s may be patterned such that a conductive structure of the transistor may be formed dielectrically spaced above the epitaxial layer. In particular, the fabrication process may include patterning the dielectric and conductive layers to form the structures of the transistor. As such, the fabrication process of a bipolar transistor may further include formation of resist pattern masks and etching processes.
As stated above, silicon nitride may be used to during the fabrication of a bipolar transistor. Such a material may serve as an etch stop during the patterning of the overlying conductive layer. In some cases, the silicon nitride layer may serve to closely control the formation of the opening formed through the dielectric layers to the underlying epitaxial layer by first etching the nitride layer and then etching the silicon dioxide layer. In order to reduce the thermal budget of the fabrication process, however, the deposition of the nitride layer is often limited to a low-temperature process, specifically at temperatures less than approximately 400xc2x0 C. One manner with which to deposit at such a low temperature is to use a plasma enhanced chemical vapor deposition (PECVD) process. However, nitride deposited using a PECVD process at relatively low temperatures is undesirably porous and easily deteriorates upon exposure to relatively dilute etch chemistries. Consequently, control of etching the nitride layer without substantially etching portions of underlying layers is difficult. In addition, a low-temperature deposited PECVD nitride layer may not adequately serve as an etch stop layer since the layer will be more susceptible to being etched at a faster rate than a high-temperature deposited nitride layer.
In addition, nitride is not typically deposited in uniform conformal manner using a low-temperature PECVD deposition process. In particular, PECVD nitride deposited at low temperatures typically deposits more material along horizontal surfaces of an underlying topography than along vertical surfaces of an underlying topography. For example, in some cases, low-temperature PECVD nitride deposited along a vertical surface of an underlying topography may include a thickness that is approximately 40% of the thickness of the PECVD nitride layer arranged along a horizontal surface of the underlying topography. As such, regions of the underlying topography including vertical surfaces may be exposed more quickly during an etch process than regions of the topography including horizontal surfaces. Consequently, the etch process used to remove the PECVD nitride layer may undesirably etch vertical portions of the underlying topography while portions of the PECVD nitride layer upon the horizontal surfaces of the underlying topography are being removed. The etching of such portions of the underlying topography may undesirably remove portions of device structures, affecting the functionality of the device.
In some cases, bipolar transistors may be fabricated adjacent to CMOS transistors to form a transistor commonly referred to as a xe2x80x9cBiCMOS transistor.xe2x80x9d In such an embodiment, the gate structures of the CMOS transistors are typically formed prior to the bipolar transistors and therefore, the nitride layer may be deposited above the gate structures of the CMOS devices. In cases in which less nitride is deposited on the sidewalls of the gate structures than adjacent horizontal surfaces, the gate structures may be undesirably etched during the removal of the nitride layer. In addition, BiCMOS transistors may be susceptible to a larger accumulation of nitride material in between the transistors due to the large aspect ratio of spacings between the transistors and the nonconformal deposition characteristics of PECVD silicon nitride. Consequently, the etch process of the nitride layer may need to be extended in order to remove the entire nitride layer, particularly in between the transistors. Such an extension of the etch process may further deteriorate the gate structures and other structures arranged laterally adjacent to the transistors.
Therefore, it would be advantageous to develop a method for fabricating a bipolar transistor that overcomes one or all of the aforementioned problems. In particular, it would be beneficial to develop a method for fabricating bipolar transistor in less processing steps than the conventional method. In addition, it would be advantageous to develop an improved method for controlling the removal of exposed portions of dielectric layers within a bipolar transistor fabrication process. In particular, it would be beneficial to develop a bipolar fabrication process which does not damage structures within the topography of the transistor during the removal of dielectric layers.
The problems outlined above may be in large part addressed by an improved method for fabricating a bipolar transistor. In particular, the aforementioned problems may be addressed by using different materials and/or process sequences than those used in conventional methods to fabricate a bipolar transistor. For example, in some cases, a method for fabricating a bipolar transistor as described herein may include patterning an epitaxial layer to expose one or more regions of a semiconductor topography prior to the deposition of an intermediate layer upon the exposed regions of the semiconductor topography and remaining portions of the epitaxial layer. In other cases, the intermediate layer may be deposited upon an unpatterned epitaxial layer. In such an embodiment, the epitaxial layer may be subsequently patterned to expose one or more regions of the semiconductor topography.
In some embodiments, the one or more exposed regions of semiconductor topography may include one or more transistors formed within the semiconductor topography. In such a case, the method may include conformally depositing the intermediate layer above and about the one or more transistors such that the thickness of the intermediate layer is substantially uniform along peripheries of the one or more transistors and in spacings between the one or more transistors. Such a conformal deposition of the intermediate layer may generate a thickness variation of less than approximately 20%, for example, across the semiconductor topography. An intermediate layer, in such an embodiment, may include amorphous silicon, polysilicon, LPCVD (low pressure chemical vapor deposition) nitride, or any other material that includes such uniform deposition characteristics. In such an embodiment, the intermediate layer may be doped or substantially undoped. In other embodiments, the method may include depositing the intermediate layer above and about the one or more transistors in a non-conformal manner such that the thickness of the intermediate layer is substantially non-uniform along peripheries of the one or more transistors and in spacings between the one or more transistors. The intermediate layer, in such an embodiment, may include silicon nitride, for example, or any other material that includes such non-uniform deposition characteristics.
In some cases, the method may additionally include exposing the intermediate layer to a rapid thermal anneal subsequent to the deposition of the intermediate layer. In other cases, the method may be substantially absent of such an anneal process. In any embodiment, the method may additionally include patterning an opening within the intermediate layer using a resist mask. Furthermore, the method may include exposing the semiconductor topography to a stripping process such that the resist mask may be removed and portions of the intermediate layer may be exposed. In such an embodiment, the intermediate layer may include a material substantially etch resistant to the stripping process, such as, for example, doped or substantially undoped amorphous silicon, polysilicon, or LPCVD silicon nitride.
In any of the embodiments described above, the method may further include forming an emitter structure of the bipolar transistor above and within the intermediate layer. In particular, the method may include depositing a conductive layer above the intermediate layer and subsequently patterning one or both of the layers to form conductive emitter structure of the bipolar transistor. For example, in some embodiments, forming the emitter structure may include patterning the conductive layer and respective underlying portions of the intermediate layer using substantially similar etch process parameters. In such an embodiment, the intermediate layer may include substantially similar etch characteristics as the conductive layer. For example, the conductive layer may include doped polysilicon, while the intermediate layer may include doped or substantially undoped polysilicon. Other materials having substantially similar etch characteristics, however, may be used for the intermediate layer and conductive layer in such an embodiment. For example, the conductive layer and/or intermediate layer may include doped or substantially undoped amorphous silicon.
In other embodiments, forming the emitter structure may include patterning the conductive layer and respective underlying portions of the intermediate layer using substantially different etch process parameters. In such an embodiment, the intermediate layer may include substantially different etch characteristics than the conductive layer. For example, the intermediate layer may include silicon nitride, while the conductive layer may include doped polysilicon or amorphous silicon. Other materials having substantially different etch characteristics, however, may be used for the intermediate layer and conductive layer in such an embodiment. In either embodiment, patterning the conductive layer may include a plurality of pattern steps. For example, patterning the conductive layer may include patterning the layer at a first width and then patterning the layer at a relatively narrower width. In other embodiments, the conductive layer may be patterned in a single patterning step.
Consequently, a semiconductor topography with a bipolar transistor having a dielectric spacer interposed between an epitaxial layer and a emitter structure is provided. In some embodiments, the dielectric spacer may include the intermediate layer arranged below the emitter structure. As such, the dielectric spacer may, in some embodiments, include an upper layer with substantially similar etch characteristics as the emitter structure. In other embodiments, the dielectric spacer may include an upper layer with substantially different etch characteristics than the emitter structure. In either embodiment, a lateral dimension of the upper layer may be bound by sidewall surfaces of the emitter structure. In some cases, the dielectric spacer may further include a lower layer including substantially different etch characteristics than the upper layer. In such an embodiment, a lateral dimension of the lower layer may be narrower than the lateral dimension of the upper layer.
In some cases, the method described herein may include etching a first dielectric layer in alignment with a patterned base of the bipolar transistor while simultaneously etching a second dielectric layer in alignment with a patterned emitter structure of the bipolar transistor. In some cases, the patterned base may include a width greater than a width of the patterned emitter structure. In other embodiments, however, the patterned base may include a width substantially similar to the width of the patterned emitter structure. In some cases, such a method may include depositing the second dielectric layer upon the patterned base and depositing a first overlying layer upon the second dielectric layer. In addition, the method may include etching an opening within the first overlying layer and the second dielectric layer. Moreover, the method may include depositing a second overlying layer within the opening and upon the first overlying layer prior to the step of etching the first and second dielectric layers.
In some embodiments, the method may further include patterning the first and second overlying layers to form the patterned emitter structure. In such a case, the first and second overlying layers may each include doped polysilcon, for example. However, other conductive materials may, however, be used for each or both of the layers. In other embodiments, the method may include patterning the second overlying layer to form the patterned emitter structure. In such an embodiment, the step of etching the second dielectric layer may further include etching the first overlying layer in alignment with the patterned emitter structure. In some cases, the first overlying layer, in such an embodiment, may include undoped polysilcon. In other cases, the first overlying layer may include silicon nitride. Other dielectric materials may, however, be used for such a layer, however.
In some cases, the methods described herein may be included in a method for fabricating a semiconductor device comprising a bipolar transistor. As such, a method for fabricating such a semiconductor device may further include forming a plurality of device structures, such as CMOS transistors and/or resistors adjacent to the bipolar transistor. In some embodiments, the method may include forming a plurality of resistors upon a semiconductor topography during the formation of the bipolar transistor structure. For example, the plurality of resistors may be formed simultaneously with the emitter structure of the bipolar transistor. Alternatively, the plurality of resistors may be formed separately from the bipolar transistor. In some cases, the method may include forming a plurality of resistors subsequent to depositing the intermediate layer of the bipolar transistor upon a patterned epitaxial layer. In particular, a plurality of resistors may be formed above one or more regions of the semiconductor topography from which the epitaxial layer has been removed. In some cases, forming the plurality of resistors may include forming a conductive layer above the intermediate layer and patterning the conductive layer and respective underlying portions of the intermediate layer to form a transitional resistor structure. The transitional resistor structure may then be patterned to form the plurality of resistors. Alternatively, forming the plurality of resistors may be conducted in a single patterning step. In some cases, the transitional resistor structure may be patterned such that the plurality of resistors have a common dielectric layer. In some embodiments, the common dielectric layer may include one or more materials substantially similar to the dielectric spacer of the bipolar transistor.
There may be several advantages to fabricating a bipolar transistor using the method described herein. In particular, a bipolar transistor may be fabricated in fewer process steps than the conventional method for forming bipolar transistors. Furthermore, additional structures may be concurrently formed upon the semiconductor topography with the bipolar transistor. For example, resistors may be formed concurrently with the bipolar transistors. As a result, production throughput of the fabrication process may increase and material usage may decrease since fewer layers will have to be deposited and etched. Consequently, fabrication costs may be reduced. Another advantage of the method described herein is that structures and layers arranged within the semiconductor topography may not be damaged by the dielectric removal process of the bipolar fabrication process. For example, the method may prevent CMOS transistors arranged within the topography from being damaged. Consequently, the functionality of the device may not be affected by the fabrication of the bipolar transistor and therefore, production yield may be increased. In addition, the method described herein offers a manner in which the portion of the epitaxial layer adjacent to the conductive emitter structure is prevented from being substantially etched. Consequently, the resistance of a contact structure formed upon such a portion of the epitaxial layer may be reduced.